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COE561 - Digital System Design and Synthesis

Course Description

Design representations, levels of abstraction & domains, Digital system design methodologies, Hardware Description Languages (HDLs), Modeling of Digital Systems using HDLs, High Level Synthesis – Internal representation (CDFG), Scheduling, Allocation & Binding, Controller and Data Path synthesis, Logic Synthesis – Two-level & Multi-level logic synthesis, Sequential logic synthesis (FSM synthesis), Technology Mapping- Library binding approaches, some case studies. The course emphasizes hands on experience through the use of available synthesis tools.


Semester Instructor(s)
COE561 - Fall 2006/2007
  • Dr. Aiman H. El-Maleh
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